BASIC DESIGN FLOW DIAGRAM
We will to go through Each stage ( Each box) & describe 1 or 2 lines for quick under standing .
Understanding Specification. :
Every ASIC design should have some specific requirement about functionality and its performance . So Designers Should understand about the functionality and other requirements .
RTL coding :
As I said before Specification understanding is mandatory to write specific RTL code for Specific ASIC design .Its very difficult to write /define the code with out knowledge of ASIC specifications ( Specification like data transfer between the registers & Data connectivity between modules etc...)
Generally RTL ( Register Transfer Level) code will be written in Verilog , VHDL or System Verilog, Being the part of RTL code will write some basic constraints for synthesis (Like clock creation , Asynchronous /Synchronous groups , Case analysis )
Synthesis :
Synthes is the process of converting RTL code to Gate level Netlist with the help of Library files . Std.Cell / Memory / Macro libraries & Technology libraries are needed for synthesis .
DFT :
Scan insertion will be done after logic Optimization & To Make Scan insertion done completely designs & Scan coverage should be around 99 % above . Need to find out logic or set of flops which are not part of scan logic. Please verify the list of flops ( which are not part of scan coverage ) with DFT team to double check .
Floorplan & Power Planning :
All Macro Placement ,Power Planning ,Tap Cells & End Cap cells will be placed . Make sure there are no Macro overlaps at Floor Planning .
Placement :
All the Std.Cell are going to place part of Core Area , Congestion and Timing will be checked at Placement . Make Sure there are no overlaps at end of Placement & Check Legality should be clean.
CTS :
Clock should reach to all sequential elements with minimum skew and Minimum Latency . Will use different type of CTS ones like conventional CTS , MSCTS & Mesh structure CTS . Will Clock Tree Optimization after CTS implementation .
Post Cts Optimization :
Will execute data path Optimization after proper clock tree structure . Will do Hold & Setup Optimization with Propagated clocks .
Route :
Finally design is routed with all the Available Metal layers & Make sure design routed with less number of Shorts & DRC's .
SignOff Flows :
Will execute different kind of Signoff flows after Route Like STA , DRV checks , FEV , DRC , LVS and PTPX .
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