Perfectsilicon VLSI basics

           Isolation cells are placed  between two power domains . These cells are introduced at Synthesis stage to isolate the logic from Power ON/OFF domain ( Gated Domain) to AON  Domain .           Lets  assume PD_1 and PD_2 is two power domains  and Signal passing between from PD_1 to PD_2 .       At Normal conditions there is no issues , its simply passes the signal from PD_1 to PD_2  either 0 or 1  value based on PD_1 conditions But when PD_1 is Off & PD_2 condition which value will passes to PD_2 domain ?  The value of signal is either 0 or 1  not sure which one will passes , Hence its corrupt the functionality.            To avoid this situvation we will use ISOLATION cells between the power OFF domain to other domains as seen in below .              In normal conditions ISOALTION cell a...

   There are couple of physical / logical cells are used other than  traditional combinational cells in the designs , Like the Below ones .  Tap cells End Cap Cells  Decap Cells  Spare cells .  Filler Cells                         Tap Cells :                 Tap Cells are used to prevent latch-up issues in the process. Traditionally these cells are used to connect VDD to the n-well and Substrate  to VSS.       Latch-Up condition :               latch-up to short circuit / low impedance path between Power and ground rails , which results to high current and damage to chip . Basically it happens due to NPN and PNP transistors combination  while formation of CMOS.  End Cap Cells :   End Cap cells are placed  on edges of block boundary . Will solve  Base ...

Floor Plan  & Power Planning         Floor Plan is one  Step to start physical design activity , Floor Plan includes the following   ones .   Definition of Die size / Block size   Macro placement  Power domain / Voltage region creation  . Boundary cells  implementation .  Tap cell placement .  End Cap cell Placement .       How to define the DIE size / Block Size :              Size of the core depends upon the total area of the logic design  and  Space for routing resources  .         Assume  "X" is the total area of the logic design .         Assume  " Y" is the % of the utilization (how area is going to be use for Std.Cell placement )         Total Area of the Block with Y% utilization is = [ (100/Y)*X  ]  Utilization :  The...