ISOLATION CELLS

-

 

         Isolation cells are placed  between two power domains . These cells are introduced at Synthesis stage to isolate the logic from Power ON/OFF domain ( Gated Domain) to AON  Domain .   

       Lets  assume PD_1 and PD_2 is two power domains  and Signal passing between from PD_1 to PD_2 . 


     At Normal conditions there is no issues , its simply passes the signal from PD_1 to PD_2  either 0 or 1  value based on PD_1 conditions But when PD_1 is Off & PD_2 condition which value will passes to PD_2 domain ?  The value of signal is either 0 or 1  not sure which one will passes , Hence its corrupt the functionality.
     
     To avoid this situvation we will use ISOLATION cells between the power OFF domain to other domains as seen in below . 
      

     In normal conditions ISOALTION cell act as Buffer , when PD_1 is OFF mode  the isolation cells clamps the output value either 0 or 1. Enable signal comes from the PMU( Power Management Unit )  module .

       ISOLATION cell as isolation enable signal that determine whether the isolation cell should provide isolation from PD_1 domain or act as buffer .  

           Generally there are two types of ISOLATION cells based on its clamp value . If its clamp value "0" , synthesis will insert by AND gate with input connected enable signal  from the PMU module .If its clamp value is "1" ,  Synthesis will insert by OR gate  with the input connected  inverted enable signal comes from PMU . Lets  see the below picture for better understanding . 

   





  Kind of Issues will see with ISO cells / Strategies  : 

  • An isolation cell required for crossing signal but its not  present in the design  or Not in the UPF .
  • An isolation cells present in the design but ISO strategy missing in the respect UPF file . 
  • An Isolation cell missing in the design but Strategy is defined in UPF file .   
  • Two different clamp values are present for the same Isolation cell in UPF file . 
  • Clamp value of the isolation cells is not matching with design vs  defined value  in UPF . 







Comments

Post a Comment

Popular posts from this blog

[ VLSI ] Special Cell ( TAP/END CAP/ DECAP/SPARE /FILLER CELLS) Description

-
   There are couple of physical / logical cells are used other than  traditional combinational cells in the designs , Like the Below ones .  Tap cells End Cap Cells  Decap Cells  Spare cells .  Filler Cells                         Tap Cells :                 Tap Cells are used to prevent latch-up issues in the process. Traditionally these cells are used to connect VDD to the n-well and Substrate  to VSS.       Latch-Up condition :               latch-up to short circuit / low impedance path between Power and ground rails , which results to high current and damage to chip . Basically it happens due to NPN and PNP transistors combination  while formation of CMOS.  End Cap Cells :   End Cap cells are placed  on edges of block boundary . Will solve  Base ...
Read more

Floor Plan Questions ...

-
What are all the inputs needed to Start Floorplan activities?   What kind of sanity checks will be done at FloorPlan ?   What is the LEF and .libs ?     Timing Information (SDC and. libs) are mandatory to start Floorplan?   What is the aspect Ratio?   Is the aspect Ratio is technology dependent?   How to create Block size based on Utilization?     Are Block X and Y dependent upon the Aspect Ratio?   Is utilization will impact the Block Size?   What is the purpose of TAP, END CAP and DECAP cells?   What are the different types of checks will do for Netlist?   Is really technologies (14 nm/7nm) will impact the floor Plan?   What is the difference between Flip Chip Vs Wire bound designs?   What do you mean by latch up?     How will TAP cells solve the latch -up problem?   How do you create power / voltage regions?   Are any guidelines to follow to define the Power / Voltage reg...
Read more