[ VLSI ] Special Cell ( TAP/END CAP/ DECAP/SPARE /FILLER CELLS) Description

Floor Plan  & Power Planning       

Floor Plan is one  Step to start physical design activity , Floor Plan includes the following  ones .  

• Definition of Die size / Block size  
• Macro placement 
• Power domain / Voltage region creation  .
• Boundary cells  implementation . 
• Tap cell placement . 
• End Cap cell Placement .      

How to define the DIE size / Block Size : 

            Size of the core depends upon the total area of the logic design  and  Space for routing resources  . 

       Assume  "X" is the total area of the logic design . 

       Assume  " Y" is the % of the utilization (how area is going to be use for Std.Cell placement )  

      Total Area of the Block with Y% utilization is = [ (100/Y)*X  ] 

Utilization :

 There are two types,

Core utilization  : Overall Std.Cell utilization entire core area .  

Row utilization  : How many Std.Cell are placed over the  row. 

     

   Aspect Ratio   : 

  

         Aspect Ratio is the one which will help to define the shape of the block . You need Horizontal & Vertical Resources to find out the proper aspect ratio .  The aspect ratio is not same for every technology ,  its going to change Based on technology & Based on Number of layers availability for routing . 

    Aspect Ratio =  Horizontal Routing Resources / Vertical Routing Resources . 

  

Macro Placement : 

 Generally Macro placement will be done Based on the following conditions . 

 

Guide lines to Macro placement : 

•  Macro to Macro connectivity 
•  Macro to Std.Cell connectivity
• Connectivity from IO's to Macro's 
• There should be at least two power / Ground stripes  should be drawn between the macro's 
• Macro pins should face to Std.Cell logic side . 
• Optimal location Based on  Available core area .
• Avoid the cris - cross connections  between macro's  & Make sure straight connections between the macros  .
• Grouping of macro's based on logical hierarchy . 

Precaution at Macro placement .  

•  There should be proper placement blockage around the macro's 
•  Soft placement blockages / Partial placement blockages between the macro. Make sure there is no  congestion and routing issues . 
• Keep out margins / Halo around the macro's to avoid the congestion near macro's .
• Macro abutment towards non pin sides . 
• Maximize more core area for Std.Cell placement . 

 

 

Some exceptional cases   macro's can be placed middle of the core area & Make sure that there is no congestion and routing issues . 

Power Domain  :  

•  Make sure you understood the power / voltage regions of your design . 
• UPF should have all the voltage / Power domain info for respective design . 
•  Along with Logical hierarchy you need to create physical shapes for the power /voltage regions . 
•   Need to estimate the area of the power / voltage region  before making any physical changes  for the domains . 
•  Make sure  we understood the  logical connectivity between the modules before physical / voltage region creation ,  other wise will see congestion / routing issues . 
• Need to check power rails for each power / voltage rails w.r.t UPF . 
•  power / voltage  Physical region should meet the respective design rules as per technologies . 
• Make sure proper power grid  for Level shifters / ISO  for all the voltage / Power  regions . 

Level shifters  and ISO cells . 

   Generally these Leve shifters are used in multi voltage designs  to convert signal from one voltage value to other voltage value. There are two types of level shifters  one is low to high &  another one is High to Low  . 

    Low to High :   Low to High level shifters are used to amplify  /boosting the signal from Low voltage domain to Hight voltage domain. ( Ex : 0.85V  to 1.0V )  . 

    

  High to Low :   High to Low level shifters are used to reduce / diminish signal from High voltage to Low voltage  domains . ( Ex : 1.0 V to 0.85 V) . 

 Two power rails are needed to connect Level shifters , One is Primary rail and another one is secondary power rail . 

 

ISO  & Power switches are needed for multi power domains . Power switches are spread across the power domain and its controlled by enable signal .  ISO cells are used to  between the ON/OFF power domains to AON domain connections . 

   

     Power switches : 

•  Part of power gating techniques , Power switch cells  & Clock gate cells are used in design .  
•  TO reduce the leakage power for specific portion of the logic , So it will helps  reduction of Leakage power / Static power . 
•  Enable signals are used along with power switches  to  OFF /  ON  for specific portion of the logic . 
• Power switches are also having two supplies , One of the primary rail  (AON ) connected to input of power switches & Derivative supply ( ON/OFF) will be output of the power switches . 

AON cells : 

• AON cells are used  part of the Power domain designs . 
• AON cells will be connected AON supply , So that even power domain is OFF stage , these AON  cells still active . 
• AON cells needed Dual power supply ( Primary & Secondary ) , Secondary supply will make sure its always AON stage even the power is off for the specific power domain .  
• Please try to avoid / Reduce AON cells in the design . 
• Make sure you have proper secondary power grid near AON cells other wise it will shoot-up lot of IR issues . 

Retention Registers :  

  Retention registers are used to store the value before power shutdown . And the values will restored after power up . Retention registers are also needed dual power supply . 

 

 

Below picture will explain the LS and ISO usage . 

  Assume PD2  is On/OFF domain , So Every out puts signal will have ISO  for PD2 domain. 

  If PD2 domain is  interacting with   different voltage domain , we need ISO followed by level Shifter . 

 

   LS needed between the Voltage regions . 

Simple Low to High  LS structure :