[VLSI] physical design Placement Interview questions

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  1. What is Physical Design flow?
  2. What are all the inputs needed to start placement run?
  3. What kind of info contains the scandef?
  4. Scandef is mandatory for placement run?
  5. What are the reasons for congestion issues?
  6. How to resolve the congestion issues?
  7. What is the keep out margin?
  8. What is the difference between Global and detailed placement?
  9. If its multi power/ voltage design, how do you place the LS and ISO cells?
  10. Are there any precautions to be taken care for LS and ISO placement?
  11. How SDC will impact the placement? Any two examples.
  12. What are the DRV rules?
  13. How do you fix the DRV violations?  what is the priority of DRV fixes …?
  14. Is the placement impact DRV violations?
  15. Is the constraints impact the DRV violations.
  16. What are all the challenges you faced at Placement stage?
  17. What are the issues / challenges are seen at Multi voltage designs?
  18. If design having both congestion and timing issues, which one you prefer to fix first?
  19. How do you resolve the congestion issues between the macros?
  20. Is the don’t use cells impact your placement?
  21. What kind of techniques is used to fix the timing issues at placement?
  22. Why clock is ideal at Placement and Floor Plan stage?
  23. What are the spare cells? why are we using at Placement stage?
  24. If design is violating more than 3000 paths, How do you analyze the reports?
  25.  What kind of checks at end of the placement ?

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