STA interview questions .....

1. What is the STA analysis?
2. What kind of inputs needed to start Prime Time?
3. What is the difference between StarRC SPEF and ICC2 SPEF?
4. How do you resolve linking issues?
5. What is PARA-006 Issues?
6. What is target Library?
7. What is link library?
8. What is the difference between False Paths Vs Disable timing paths?
9. How generated clocks will define?
10. How to check constraints quality?
11. What are the timing loops?
12. What will happen with timing loops?
13. How to resolve un-clocked  sequential ?
14. What is the purpose of set_max_delay constraints?
15. What is MPW? How to fix MPW?
16. As STA engineer, which will prefer fix before starting the ECO’s of the partition?
17. What kind of checks will do before timing fixes?
18. What is the linking issues code in Log files?
19. How do u check quality of parasitic files?
20. What is RC-011 warning in log files?
21. Can we create clock definitions on combo cells?
22. Can u draw circuit for generated clocks?
23. Is cross talk going to impact setup or hold?
24. What is CRPR?
25. How CRPR is going to impact your design  ?
26. What is arrival time?
27. What is required time?
28. how do you fix clock gate violations?
29. what is the meaning of set_driving_cell?
30.  What kind of latency is good for design, Higher latency or lower latency?
31. What do you mean by global skew or local skew ?
32.  What is the setup & Hold time?
33. How can we avoid setup & Hold timing issues?
34. What the purpose of timing constraints?
35. What is the corners / modes?
36. What is the difference between SS and FF timing analysis
37. How do you read timing models for Hierarchical model designs?
38.  What is the difference between PnR spef Vs QRC spec?
39. What kind of variations will be see between two corners?
40. What is the effect of temperature inversion effect?
41. Is any constraints will be defined in .lib files?
42.  What is the difference wire load models Vs SPEF files?
43.  What is the difference between Pre and Post Layout STA?  Is the inputs files are going to change between the two models?
44.  What is the duty cycle distortion?  how to improve?
45.  How to fix the cross talk?
46. How will latency impact Setup / Hold timing?
47. What is anchor buffer?
48.  What is the difference between CCS and NLDM models?
49. Which model is more accurate between CCS and NLDM models ?
50. What kind of information contains in. libs ?