Perfectsilicon VLSI basics

   There are couple of physical / logical cells are used other than  traditional combinational cells in the designs , Like the Below ones .  Tap cells End Cap Cells  Decap Cells  Spare cells .  Filler Cells                         Tap Cells :                 Tap Cells are used to prevent latch-up issues in the process. Traditionally these cells are used to connect VDD to the n-well and Substrate  to VSS.       Latch-Up condition :               latch-up to short circuit / low impedance path between Power and ground rails , which results to high current and damage to chip . Basically it happens due to NPN and PNP transistors combination  while formation of CMOS.  End Cap Cells :   End Cap cells are placed  on edges of block boundary . Will solve  Base ...

What is Physical Design flow? What are all the inputs needed to start placement run? What kind of info contains the scandef? Scandef is mandatory for placement run? What are the reasons for congestion issues? How to resolve the congestion issues? What is the keep out margin? What is the difference between Global and detailed placement? If its multi power/ voltage design, how do you place the LS and ISO cells? Are there any precautions to be taken care for LS and ISO placement? How SDC will impact the placement? Any two examples. What are the DRV rules? How do you fix the DRV violations?  what is the priority of DRV fixes …? Is the placement impact DRV violations? Is the constraints impact the DRV violations. What are all the challenges you faced at Placement stage? What are the issues / challenges are seen at Multi voltage designs? If design having both congestion and timing issues, which one you prefer to fix first? How do you resolve the congestion issues between the macros? Is t...

What is the STA analysis? What kind of inputs needed to start Prime Time? What is the difference between StarRC SPEF and ICC2 SPEF? How do you resolve linking issues? What is PARA-006 Issues? What is target Library? What is link library? What is the difference between False Paths Vs Disable timing paths? How generated clocks will define? How to check constraints quality? What are the timing loops? What will happen with timing loops? How to resolve un-clocked  sequential ? What is the purpose of set_max_delay constraints? What is MPW? How to fix MPW? As STA engineer, which will prefer fix before starting the ECO’s of the partition? What kind of checks will do before timing fixes? What is the linking issues code in Log files? How do u check quality of parasitic files? What is RC-011 warning in log files? Can we create clock definitions on combo cells? Can u draw circuit for generated clocks? Is cross talk going to impact setup or hold? What is CRPR? How CRPR is going to impact your d...

What are all the inputs needed to Start Floorplan activities?   What kind of sanity checks will be done at FloorPlan ?   What is the LEF and .libs ?     Timing Information (SDC and. libs) are mandatory to start Floorplan?   What is the aspect Ratio?   Is the aspect Ratio is technology dependent?   How to create Block size based on Utilization?     Are Block X and Y dependent upon the Aspect Ratio?   Is utilization will impact the Block Size?   What is the purpose of TAP, END CAP and DECAP cells?   What are the different types of checks will do for Netlist?   Is really technologies (14 nm/7nm) will impact the floor Plan?   What is the difference between Flip Chip Vs Wire bound designs?   What do you mean by latch up?     How will TAP cells solve the latch -up problem?   How do you create power / voltage regions?   Are any guidelines to follow to define the Power / Voltage reg...